Typical semiconductor memories are fabricated on semiconductor substrates including arrays of a large number of physical memory cells. In general, one bit of binary data is represented as a variation of a physical parameter associated with a memory cell. Commonly used physical parameters may include, for example, threshold voltage variation of a metal-oxide-semiconductor field effect transistor (MOSFET) in a memory cell of the memory device due to the amount of charge stored in a floating gate or a trap layer in non-volatile electrically erasable programmable read-only memory (EEPROM), resistance variation of a phase change memory (PCM) element in phase-change random access memory (PCRAM) or ovonic unified memory (OUM), and charge storage variation in volatile dynamic random access memory (DRAM).
Some issued U.S. patents which may be relevant to an understanding of the invention by the skilled artisan include, but are not limited to, U.S. Pat. No. 7,567,473 entitled “Multi-level Memory Cell Utilizing Measurement Time Delay as the Characteristic Parameter for Level Definition,” U.S. Pat. No. 7,602,631 entitled “Multi-level Memory Cell Utilizing Measurement Time Delay as the Characteristic Parameter for Level Definition,” U.S. Pat. No. 7,602,632 entitled “Multi-level Memory Cell Utilizing Measurement Time Delay as the Characteristic Parameter for Level Definition,” U.S. Pat. No. 7,480,184 entitled “Maximum Likelihood Statistical Method of Operations for Multi-bit Semiconductor Memory,” U.S. Pat. No. 5,936,906 entitled “Multilevel Sense Device for Flash Memory,” U.S. Pat. No. 6,009,040 entitled “Apparatus and Methods for Controlling Sensing Time in a Memory Device,” U.S. Pat. No. 6,307,783 entitled “Descending Staircase Read Technique for a Multilevel Cell NAND Flash Memory Device,” U.S. Pat. No. 6,956,779 entitled “Multistage Autozero Sensing for a Multilevel Non-volatile Memory Integrated Circuit System,” U.S. Pat. No. 6,961,266 entitled “Method of Programming-Reading Multi-Level Flash Memory Using Sensing Circuit,” U.S. Pat. No. 6,975,539 entitled “Digital Multilevel Non-volatile Memory System,” U.S. Pat. No. 7,142,464 entitled “Apparatus and Methods for Multi-level Sensing in a Memory Array,” U.S. Pat. No. 7,532,529 entitled “Apparatus and Methods for Multi-level Sensing in a Memory Array,” U.S. Pat. No. 7,359,246 entitled “Memory Device with a Ramp-Like Voltage Biasing Structure Base on a Current Generator,” and U.S. Pat. No. 7,580,297 entitled “Readout of Multi-Level Storage Cells,” the respective disclosures of which are incorporated herein by reference in their entireties for all purposes.
Multi-level cell (MLC) memory architectures having the capability of storing more than one bit of binary information in a given memory cell are well known. However, conventional sensing schemes for reading the respective states of MLCs in a memory array are often complex, slow, and inflexible, among other disadvantages, and thus undesirable.